1. Field of the Invention
The present invention relates to random access memory technology and architecture, and more particularly to reducing gate leakage and threshold voltage fluctuation in memory cells by employing threshold voltages in a plurality of operational regimes.
2. Description of the Related Art
Static memory storage devices are subjected to more constraints at low voltages. With the portability of active or switching memory devices, power becomes a greater concern with higher performance requirements since power levels are generally lower and limited by portable power storage devices. These difficulties make the design of storage cells for portable applications more challenging.
Static random access memories (SRAM) typically include a cell including six transistors that stores data and can be read from and written to without a refresh cycle. SRAM may be employed in high performance applications e.g., in caches, microprocessors, memory buffers in ASICs, etc.
Designing complementary metal oxide semiconductor (CMOS) static random access memory (SRAM) cells for high performance becomes particularly challenging at low power supply voltages, which are typically employed for portable applications. The data stored in a cell becomes increasingly vulnerable to a read upset and other stability problems at these low power voltages. In addition, the scalability of the supply voltage is also limited for conventional CMOS SRAM cells, due to dopant fluctuations in small-geometry cell transistors.
Exponentially increasing leakage, higher demands on SRAM performance at lower operating voltages and data retention stability in the presence of severe threshold voltage fluctuations are performance issues of newer generations of SRAM devices.
These issues were typically addressed by providing lower supply voltages for transistor gates and/or thicker gate oxide thicknesses. However, lower supply voltages may result in data stability problems, and as a result lower performance (slower, etc.) are experienced in SRAM cells. In addition, thicker gate oxides result in severe short channel effects, i.e., the gate exercises less control in its ability to turn off the transistor.
As devices shrink, tunneling currents across gate oxides increase exponentially by scaling to small geometries, e.g., gate oxide thickness. Furthermore, as the device geometries shrink, the number of impurity atoms decreases and as a result their statistical variation in number and position increases; hence, reducing the numbers of electron donors or acceptors in the smaller geometry (structure).
Bulk charge contributes to the threshold voltage of a MOSFET device, and fluctuates with respect to the number of doping atoms/impurities in the device, which in turn causes fluctuation in the threshold voltage. The threshold voltage is the gate voltage at which a MOSFET device turns on.
These fluctuations cause mismatches in inverters and NFETs in SRAMS and result in variability of the SRAM cell's characteristics, which degrades cell static noise margins. Static noise margins are defined as a minimum static noise voltage required to flip the state of the SRAM cell during a read access.
Therefore, a need exists for a structure and method, which reduces or eliminates gate leakage and threshold voltage fluctuation in SRAM cells in both idle and active modes.